KS32C50100 risc microcontroller 32-bit timers 11-1 11 32-bit timers overview the KS32C50100 has two 32-bit timers. these timers can operate in interval mode or in toggle mode. the output signals are tout0 and tout1, respectively. you enable or disable the timers by setting control bits in the timer control register, tcon. an interrupt request is generated whenever a timer count-out (down count) occurs. interval mode operation in interval mode, a timer generates a one-shot pulse of a preset timer clock duration whenever a time-out occurs. this pulse generates a time-out interrupt that is directly output at the timer's configured output pin (toutn). in this case, the timer frequency monitored at the toutn pin is calculated as: f tout = f mclk / timer data value toggle mode operation in toggle mode, the timer pulse continues to toggle whenever a time-out occurs. an interrupt request is generated whenever the level of the timer output signal is inverted (that is, when the level toggles). the toggle pulse is output directly at the configured output pin. using toggle mode, you can achieve a flexible timer clock range with 50% duty. in toggle mode, the timer frequency monitored at the toutn pin is calculated as follows: f tout = f mclk / (2 * timer data value) figure 11-1 timer output siganl timing interval mode toggle mode (initial toutn is 0) f tout time-out time-out time-out f tout
32-bit timers KS32C50100 risc microcontroller 11-2 timer operation guidelines the block diagram in figure 11-2 shows how the 32-bit timers are configured in the KS32C50100. the following guidelines apply to timer functions. ? when a timer is enabled, it loads a data value to its count register and begins decrementing the count register value. ? when the timer interval expires, the associated interrupt is generated. the base value is then reloaded and the timer continues decrementing its count register value. ? if a timer is disabled, you can write a new base value into its registers. ? if the timer is halted while it is running, the base value is not automatically re-loaded. figure 11-2 32-bit timer block diagram auto re-load tmod.tmdn tmod.tclrn port 16, port 17 data out iopcon.toenn toutn intpnd and intmsk interrupt request f mclk tmod.ten 32-bit timer data register (tdatan) 32-bit timer count register (tcntn) [down counter] pnd pulse generator
KS32C50100 risc microcontroller 32-bit timers 11-3 timer mode register the timer mode register, tmod, is used to control the operation of the two 32-bit timers. tmod register settings are described in figure 11-3. table 11-1 tmod register register offset address r/w description reset value tmod 0x6000 r/w timer mode register 32?h00000000 figure 11-3 timer mode register (tmod) 31 1 0 t c l r 0 t m d 0 t c l r 1 6 5 3 2 4 t m d 1 t e 1 t e 0 [0] timer 0 enable (te0) 0 = disable timer 0 1 = enable timer 0 [1] timer 0 mode selection (tmd0) 0 = interval mode 1 = toggle mode [2] timer 0 initial tout0 value (tclr0) 0 = initial tout0 is 0 in toggle mode 1 = initial tout0 is 1 in toggle mode [3] timer 1 enable (te1) 0 = disable timer 1 1 = enable timer 1 [4] timer 1 mode seletion (tmd1) 0 = interval mode 1 = toggle mode [5] timer 1 initial tout1 value (tclr1) 0 = initial tout1 is 0 in toggle mode 1 = initial tout1 is 1 in toggle mode
32-bit timers KS32C50100 risc microcontroller 11-4 timer data registers the timer data registers, tdata0 and tdata1, contain a value that specifies the time-out duration for each timer. the formula for calculating the time-out duration is: (timer data + 1) cycles. table 11-2 tdata0 and tdata1 registers register offset address r/w description reset value tdata0 0x6004 r/w timer 0 data register 0x00000000 tdata1 0x6008 r/w timer 1 data register 0x00000000 figure 11-4 timer data registers (tdata0, tdata1) 31 0 timer data [31:0] timer 0/1 data value
KS32C50100 risc microcontroller 32-bit timers 11-5 timer count registers the timer count registers, tcnt0 and tcnt1, contain the current timer 0 and 1 count value, respectively, during normal operation. table 11-3 tcnt0 and tcnt1 registers register offset address r/w description reset value tcnt0 0x600c r/w timer 0 count register 0xffffffff tcnt1 0x6010 r/w timer 1 count register 0xffffffff figure 11-5 timer count registers (tcnt0, tcnt1) 31 0 timer count [31:0] timer 0/1 count value
32-bit timers KS32C50100 risc microcontroller 11-6 notes
|
